I2S
Let´s take a look into the I2S specification and let us try to realize the hardware and the software to play audio files with an FPGA.
Last updated
Let´s take a look into the I2S specification and let us try to realize the hardware and the software to play audio files with an FPGA.
Last updated
The Inter-IC Sound Interface (I2S for short) was developed by Philips to transmit digital audio data via a serial interface between different ICs (e.g. from a processor to a DAC). The interface uses the following signals for data transmission:
Only audio data is transmitted via the I2S. Additional data, such as the configuration of individual bus users, are transmitted via other interfaces. A data transfer always takes place in one direction and between two bus users, whereby the bus user must act as a master and is responsible for generating the clock signals. In complex systems consisting of several transmitters and receivers, the clock signals are generated by an external bus master and the respective transmitter generates the data.
All data are transmitted as two's complement and MSB First. If there is a positive difference in the word widths of the receiver and transmitter (i.e. if the word width of one participant is smaller than that of the other), the remaining bits are filled with 0. If the difference is negative (ie the word width of one participant is larger than that of the other), the remaining bits are ignored. According to the specification, the data can be synchronized to the positive or the negative clock edge, whereby the data is always read in with the negative clock edge.
The WS signal selects the active channel and all data within a low or high phase are assigned to the respective channel. The following applies:
WS = 0 – Channel 1 (Left)
WS = 1 – Channel 2 (Right)
The WS signal must always be changed one clock cycle before the MSB of the next data word so that the receiver can read the data into the correct channel. The clock frequency of the WS signal usually corresponds to the sampling frequency of the audio signal.
In the following examples, I will gradually introduce the individual development steps for the development of an I2S-IP core for a connection to the ZYNQ Processing System.
You can also find the whole project in my GitLab-Repository.
Signal
Function
Description
SCK
Serial clock
Clock line for data transmission.
SD
Serial data
The individual bits of each data word are transmitted via this line.
WS
Word select
Defines the length of the transmitted data word. It is used to mark the right or left audio channel.
